Semiconductor integrated circuits (ICs) are typically fabricated by implanting transistors into the surface of a semiconductor (e.g., Silicon (Si)) and interconnecting the transistors as is appropriate (e.g., as dictated by a circuit design) with metal signal lines that are routed above the semiconductor surface. Semiconductor processes that manufacture digital ICs emphasize the ability to tightly pack as many transistors as is feasible upon a large semiconductor surface. Current day digital IC manufacturing processes can integrate as many as forty million transistors onto a single thumbnail or larger sized “chip” of semiconductor material.
Because, for digital ICs, an immense number of transistors can be integrated onto a wide semiconductor surface—and because transistors located far away from each other on the semiconductor surface often need to be connected—the circuit of metal lines or wires (also referred to as “wiring”) that are routed above the semiconductor surface in order to properly interconnect the transistors is extremely complex. The complexity is handled, at least in part, through the manufacture of multiple layers of metal wires above the semiconductor surface. For example, current manufacturing processes can employ as many as eight planar levels above the semiconductor surface where metal wires may be located for the purposes of connecting at least a pair of transistors.
Because of the economic benefits of integration, a great deal of attention has been placed on the ability to place analog circuitry onto the same semiconductor chip with digital circuitry. Analog circuitry tends to be more sensitive to noise than digital circuits. As a consequence, in the design and fabrication of both “mixed signal” ICs (where considerable portions of both analog and digital circuitry reside on the same semiconductor chip) or “largely digital” ICs (where a large, comprehensive digital IC includes one or more region(s) of analog circuitry), attempts are made to deliberately partition the analog circuitry from the digital circuitry on the semiconductor surface. Here, the incessant “switching” activity of digital circuitry can create noise (e.g., through supply, reference, ground or even signal lines) that—if able to reach the analog circuit in sufficient strength—could cause the analog circuit to inadequately perform its corresponding function.
By separately partitioning the analog circuitry from the digital circuitry on the semiconductor surface, a degree of isolation is achieved that thwarts the propagation of digitally induced noise into the noise sensitive analog circuitry. Thus, it is not uncommon when observing the layout of an IC having both digital and analog circuit functions to find “islands” of an analog circuitry. Often, analog circuitry is placed at an edge of the semiconductor surface to prevent digital circuitry from residing around all sides of the analog circuitry on the semiconductor surface. Moreover, in order to further provide some degree of isolation between the digital and analog circuitry, digital signal lines are often designed so as to not to “pass over” the analog circuitry. That is, recalling that multiple vertical layers are made available for the routing of wires between transistors, often, digital signal wires are designed so as not to pass over a region of a semiconductor surface where analog circuitry resides.
As a consequence, much of the higher levels where wires could potentially be routed are left empty. FIG. 1 shows an exemplary illustration 100. According to FIG. 1, five wiring layers M1 102a through M5 102e are observed upon a semiconductor surface 101. A region 105 of the semiconductor surface (meted out by lines 105a and 105b) is where the transistors of an analog circuit are located. As such, region 105 and the volumetric space above region 105 can be viewed as an analog region of the IC. Note that only the first two wiring layers M1 102a and M2 102b are used to interconnect the transistors of the analog circuit (as well as provide whatever input(s)/output(s) are needed to/from the analog circuitry).
This is often a circumstance of the analog circuitry having a less aggressive transistor packing density than the digital circuitry and/or the analog partition scheme itself. That is, because analog transistors tend to be more spread out on the semiconductor surface 101 than digital transistors, less vertical jumps are needed by the transistor interconnect wiring; and/or, the partitioning of the analog transistors into “their own” dedicated region 105 largely prevents the implementation of long analog wire runs across a wide expanse of the semiconductor chip that necessitate a vertical jump is wiring level (e.g., due to the intercept with another wire at the same level). It should be understood that the use of two wiring metal layers M1 102a and M2 102b over the expanse of the analog region 105 is only exemplary. That is, in other cases, the wire layers used for the analog circuit's internal signaling may be largely limited to only the first wiring layer M1 102a and/or various protrusions of higher layer wiring may be formed at specific locations giving the analog circuit and uneven wiring topography.
Note that the use of only a few wire layers for analog purposes and the prevention of placing digital wiring over the analog circuit causes a significant ‘void’ 104 in the useable volumetric space of the semiconductor IC. That is, because the overall wiring structure is constructed with layers of dielectric sandwiched between wire layers having metal lines for wiring, and because dielectric material is used as a default material in those regions of a wiring layer where no wiring metallurgy resides, region 104 is largely filled with dielectric material that acts as an unused filler.